Tungsten gate MOS transistor and memory cell and method of making same

ABSTRACT

A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell by silicon nitride capping and sidewall layers. The inventive methodology advantageously prevents deleterious oxidation during subsequent processing at high temperature and in an oxidizing ambient.

CROSS-REFERENCE TO PROVISIONAL APPLICATION

[0001] This application claims priority from provisional patentapplication Serial No. 60/152,126, filed Sep. 2, 1999, the entiredisclosure of which is incorporated herein by reference.

FIELD OF THE INVENTION

[0002] The present invention relates to a method of manufacturing a MOStransistor and a memory cell on a common semiconductor substrate and thedevice obtained thereby. The present invention has particular utility inmanufacturing high-density integration semiconductor memory devices,such as flash electrically erasable programmable read only memories(flash EEPROMS), with design rules of about 0.18 micron and under.

BACKGROUND OF THE INVENTION

[0003] The flash EEPROM is so named because the contents of all of thememory's array cells can be erased simultaneously at high speed. FlashEEPROMs, unlike floating gate EEPROMs which include a separate selecttransistor in each cell to provide for individual byte erasure,eliminate the select transistor and provide bulk erasure. As aconsequence, flash EEPROM cells can be made much smaller than floatinggate EEPROM cells fabricated under the same design rules, thuspermitting formation of high density memories having easy erasabilityand reprogrammability.

[0004] Conventional flash EEPROMs typically comprise a floating gatememory cell, which includes a source region, a drain region, and achannel region formed in a semiconductor substrate, usually a siliconwafer, and a floating gate formed above the substrate and locatedbetween the channel region and a control gate. Most flash EEPROM cellsuse a “double-poly” structure, wherein an upper layer formed of e.g.,polysilicon and termed “poly 2”, forms the control gate and a lowerlayer of polysilicon, termed “poly 1”, forms the floating gate. The gateoxide layer is typically about 10 nm thick and the interpoly dielectrictypically comprises a three layer composite of silicon oxide/siliconnitride/silicon oxide layers (“ONO”) of total thickness of about 25 nmor less.

[0005] In operation, to program the memory cell, typically by ChannelHot Electron (“CHE”) injection, a high voltage, such as about 10 volts,is applied to the control gate and a moderately high voltage, e.g.,about 5 volts, is applied to the drain terminal while the source andsubstrate terminals are at ground potential To erase the cell. either aSource Edge Erase (“SEE”) or a Channel Erase (“CE”) procedure can beutilized. According to the SEE procedure, a high negative voltage, suchas −10 volts, is applied to the control gate and a moderately highvoltage, e.g., about 5 volts, is applied to the source terminal whilethe drain potential floats. According to the CE procedure, a highnegative voltage, such as −10 volts, is applied to the control gate anda moderately high voltage, e.g., about 7 volts, is applied to the devicebody (e.g., a well) while the source and drain potentials float. Ineither instance, a sufficiently large electric field is developed acrossthe tunnel oxide and electrons can tunnel out from the floating gateeither at the source terminal (SEE procedure) or through the channelregion (CE procedure).

[0006] Flash EEPROM systems conventionally comprise a two-dimensionalarray of floating gate memory cells such as described above. The arraytypically includes several strings of floating gate memory transistors,each transistor being coupled to the neighboring transistor in thestring by coupling the source of one device to the drain of theneighboring device, thereby forming bit lines. A plurality of wordlines, perpendicular to the strings, each connect to the control gate ofone memory cell of each string.

[0007] A CMOS transistor, referred to as a “row selector”, is employedat one end of each word line to supply program voltage on demand to eachof the word lines. The row selecting transistor and other transistors,e.g., for power supply purposes, are formed in the semiconductor wafersubstrate concurrent with the formation of the memory cell array andtypically employ much of the same processing steps and conditions. Insome instances, the transistor, termed a “poly 2 periphery transistor”is formed on a peripheral portion of the semiconductor substrate andutilizes the “poly 2”, or upper polysilicon layer used to form thecontrol gates of the memory array cells.

[0008] In order to electrically contact the “poly 2” layer forming thegate electrode of such peripheral transistors and the control gateelectrode of the memory array cells, a layer of a refractory metal,e.g., titanium (Ti) or tungsten (W), is typically formed over the “poly2” electrode (with or without interposition of adhesion and/or barrierlayer(s)) and suitably patterned and annealed. The use of tungsten forforming such contacts is particularly attractive because tungsten—basedpolysilicon gate electrode contacts can be formed with sub-micron sizeddimensions (D. Hisamoto et al., 1995 Symposium on VLSI Technology Digestof Technical Papers, pp 115-116), and with very low sheet resistance(i.e., 1.6-3 Ω/□) when either a titanium nitride (TiN) or tungstennitride (WN_(x)) interlayer is provided between the tungsten layer andthe polysilicon gate electrode layer (D. H. Lee et al., 1995 Symposiumon VLSI Technology Digest of Technical Papers, pp 119-120; K. Kasai etal., IEDM 94, pp 497-500). However, a significant problem encounteredwith the use of tungsten as a gate electrode contact metal in memoryarray manufacture is oxidation thereof during high temperature (e.g.,about 900° C.) furnace processing under an oxidizing ambient during MOStransistor and flash memory cell fabrication.

[0009] Thus, there exists a need for a process scheme, compatible withexisting flash memory semiconductor manufacture, which allows formationof very low sheet resistance tungsten gate electrode contacts of deepsubmicron dimensions while reducing or eliminating oxidation thereofduring subsequent processing.

DISCLOSURE OF THE INVENTION

[0010] An advantage of the present invention is a method ofmanufacturing a high-density flash memory array with an improved controlgate electrode contact structure.

[0011] Another advantage of the present invention is a method ofmanufacturing a flash memory array including a control gate electrodestructure which is resistant to oxidation during high temperatureprocessing in an oxidizing ambient.

[0012] Still another advantage of the present invention is a method ofsimultaneously forming oxidation resistant tungsten-based contacts tothe gate electrode of a MOS transistor and the control gate electrode ofa memory cell of a flash EEPROM.

[0013] A still further advantage of the present invention is provisionof a high density integration flash EEPROM semiconductor device having atungsten-based gate electrode contact structure resistant to oxidation.

[0014] Additional advantages and other features of the present inventionwill be set forth in part in the description which follows and in partwill become apparent to those having ordinary skill in the art uponexamination of the following or may be learned from the practice of thepresent invention. The advantages of the present invention may berealized and obtained as particularly pointed out in the appendedclaims.

[0015] According to the present invention, the foregoing and otheradvantages are achieved in part by a method of manufacturing asemiconductor device, which method comprises:

[0016] providing a semiconductor substrate comprising silicon and havinga surface;

[0017] sequentially forming over the substrate a layer stack comprising:

[0018] a gate oxide layer (a) on the substrate surface,

[0019] an electrically conductive polysilicon layer (b) on the gateoxide layer,

[0020] a barrier material layer (c) on the polysilicon layer,

[0021] a tungsten layer (d) on the barrier material layer, and

[0022] a silicon nitride layer (e) on the tungsten layer;

[0023] selectively removing portions of layers (c)-(c) to define apattern therein exposing sidewall surfaces of layers (c)-(e);

[0024] selectively forming a silicon nitride layer (f) covering theexposed sidewall surfaces of layers (c)-(e), whereby the tungsten layer(d) is encapsulated by the combination of silicon nitride layers (e) and(f) formed on the uppermost and sidewall surfaces thereof, respectively;

[0025] selectively removing portions of polysilicon layer (b) to definea pattern therein exposing sidewall surfaces thereof in substantialvertical registry with the sidewall surfaces of layers (c)-(e); and

[0026] annealing the thus-formed layer stack at an elevated temperaturein an oxidizing ambient, whereby the silicon nitride encapsulatinglayers (e) and (f) prevent oxidation of the tungsten layer (d) duringthe annealing.

[0027] According to another aspect of the present invention, thesemiconductor device comprises a transistor, the layer stack formingcomprises forming same on at least a peripheral portion of the substratesurface, the electrically conductive polysilicon layer (b) comprises agate electrode of the transistor, and the tungsten layer (d) comprises agate electrode contact.

[0028] According to still another aspect of the present invention, themethod further comprises, after forming gate oxide layer (a) but priorto forming polysilicon layer (b), the steps of:

[0029] forming an electrically conductive polysilicon layer (a′) on thegate oxide layer (a); and

[0030] forming an interpoly dielectric layer (a″) on the polysiliconlayer (a′);

[0031] the method further comprising the step of selectively removingportions of polysilicon layer (a′) and interpoly dielectric layer (a″)to thereby expose sidewall surfaces thereof in substantial verticalregistry with the exposed sidewall surfaces of layers (b)-(e);

[0032] wherein the semiconductor device comprises a flash EEPROM,polysilicon layer (a′) comprises a floating gate electrode, polysiliconelectrode (b) comprises a control gate electrode, and tungsten layer (d)comprises a low sheet resistance control gate electrode contact.

[0033] In embodiments according to the present invention, polysiliconlayer (b) corresponds to “poly 2”, polysilicon layer (a′) corresponds to“poly 1”, the barrier material layer (c) comprises titanium nitride ortungsten nitride, the interpoly dielectric layer (a″) comprises asilicon oxide/silicon nitride/silicon oxide (“ONO”) composite, and theannealing comprises heating in a furnace in an oxygen containing ambientat a temperature of from about 800° C. to about 950° C. for from about30 min. to about 60 min.

[0034] According to a still further aspect of the present invention asemiconductor device structure comprises:

[0035] a semiconductor substrate comprising silicon and having a surfacewith at least one active device region formed therein or thereon;

[0036] a layer stack formed on the substrate surface over the at leastone active device region, the layer stack comprising, in sequence:

[0037] a gate oxide layer (a) on the substrate,

[0038] an electrically conductive polysilicon gate electrode layer (b)on the gate oxide layer,

[0039] a titanium nitride or tungsten nitride barrier layer (c) on thepolysilicon layer,

[0040] a tungsten gate electrode contact layer (d) on the barrier layer,and

[0041] a silicon nitride layer (e) on the tungsten layer, the layerstack patterned to expose sidewall surfaces of layers (b)-(e); and

[0042] a silicon nitride layer (f) covering the exposed sidewallsurfaces of layers (c)-(e), whereby the tungsten layer (d) isencapsulated by the combination of silicon nitride layers (e) and (f)formed on the uppermost and sidewall surfaces thereof, respectively,thereby preventing oxidation of tungsten layer (d) during annealingtreatment of the device structure at an elevated temperature in anoxidizing ambient.

[0043] According to an aspect of the present invention, thesemiconductor device structure comprises a transistor and the at leastone active device region is formed at least at a peripheral portion ofthe semiconductor substrate.

[0044] According to a further aspect of the present invention, the layerstack of the semiconductor device structure further comprises anelectrically conductive polysilicon layer (a′) (=“poly 1”) on the gateoxide layer (a) and a silicon oxide/silicon nitride/silicon oxidecomposite interpoly dielectric layer (a″) on the polysilicon layer (a′)and under polysilicon layer (b) (=“poly 2”), polysilicon layer (a′) andcomposite interpoly dielectric layer (a″) patterned to expose sidewallsurfaces thereof in substantial vertical registry with the sidewallsurfaces of layers (b)-(e) of the layer stack, wherein the semiconductordevice structure comprises a flash-type EEPROM, polysilicon layer (a′)comprises a floating gate electrode, polysilicon layer (b) comprises acontrol gate electrode, and tungsten layer (d) comprises a control gateelectrode contact.

[0045] Additional advantages of the present invention will becomereadily apparent to those skilled in the art from the following detaileddescription, wherein only the preferred embodiment of the presentinvention is shown and described, simply by way of illustration of thebest mode contemplated for carrying out the method of the presentinvention. As will be realized, the present invention is capable ofother and different embodiments, and its several details are capable ofmodifications in various obvious respects, all without departing fromthe present invention. Accordingly, the drawing and description are tobe regarded as illustrative in nature, and not as limitative

BRIEF DESCRIPTION OF THE DRAWINGS

[0046] FIGS. 1(a)-1(h) and 2(a)-2(h) are simplified, cross-sectionalschematic diagrams illustrating process steps for forming “poly 2”peripheral transistor and stacked-gate memory cell portions,respectively, of a flash-type EEPROM device, in accordance with anembodiment of the present invention.

[0047] It should be recognized that the various layers forming the layerstack or laminate illustrated in the appended drawing figures asrepresenting portions of EEPROM structures and devices fabricatedaccording to the inventive methodology are not drawn to scale, butinstead are drawn as to best illustrate the features of the presentinvention.

DESCRIPTION OF THE INVENTION

[0048] Referring to FIGS. 1(a) and 2(a), shown therein are layer stacksL₁ and L₂ formed on peripheral and central portions, respectively, ofthe silicon-based semiconductor substrate 1. Layer stack L₁ for formingthe peripheral transistor comprises, in sequence, a gate oxide layer 2on the upper surface of substrate 1, an electrically conductivepolysilicon gate electrode layer 3 (“poly 2”) on gate oxide layer 2, abarrier material layer 4 of titanium nitride (TiN) or tungsten nitride(WN_(x)) on polysilicon layer 3, a tungsten gate electrode contact layer5 on barrier material layer 4, and silicon nitride layer 6 on tungstencontact layer 5. Layer stack L₂ for forming a memory cell comprises, inaddition to the above described layers 2-6, a further electricallyconductive polysilicon gate electrode layer 7 (“poly 1”) formed on gateoxide layer 2 and an interpoly dielectric layer 8, typically a siliconoxide/silicon nitride/silicon oxide (“ONO”) composite, formed onpolysilicon layer 7 and below polysilicon layer 3 (“poly 2”).

[0049] Layers 2-8 typically are formed utilizing well-known oxidative,reactive, physical vapor, and/or chemical vapor deposition techniques,the details of which are omitted from the description for brevity,except as noted. A preferred method for forming barrier material layer 4comprises reactive sputtering of a titanium or tungsten target in anitrogen (N₂) containing atmosphere. The use of a tungsten target has anadvantage in that the same target can be used, in sequence, forformation of the overlying tungsten contact layer 5 by non-reactivesputtering. Tungsten contact layer 5 can also be formed by a chemicalvapor deposition process (CVD) utilizing e.g., tungsten hexafluoride(WF₆). Suitable ranges of thickness as well as preferred thicknesses foreach of the layers of the layer stacks are indicated in Table 1 below.TABLE 1 Preferred Layer Material Thickness Range, Å Thickness, Å 2Silicon oxide 25-150  70 3 Polysilicon 900-2500 1200  4 Titanium nitrideor 50-300 100 tungsten nitride 5 Tungsten 700-4000 2000  6 Siliconnitride 150-1000 700 7 Polysilicon 250-1000 500 8 Silicon oxide/ 50-300150 silicon nitride/ silicon oxide

[0050] After forming layer stacks L₁ and L₂, a bottom anti-reflectioncoating layer 9 (“BARC”) is formed atop the uppermost, silicon nitridelayer 6 of each layer stack, followed by formation thereon of apatterned photoresist layer 10, in a known manner. Then layers 4-6,respectively formed of titanium nitride or tungsten nitride, tungsten,and silicon nitride, are etched along with BARC layer 9, as by reactiveion etching (RIE), using patterned photoresist layer 10 as an etch maskand polysilicon layer 3 (poly 2) as an etch stop. After removal of thephotoresist layer 10 along with the underlying portion of BARC layer 9,the structures shown in FIGS. 1(b) and 2(b) are obtained.

[0051] Next a second silicon nitride film, at least about 1,000 Å thick,is deposited over the thus-patterned layer stacks so as to cover allexposed surfaces thereof and anisotropically etched, as by reactive ionetching, to remove a major portion of the thickness of the secondsilicon nitride film formed on the upper surface of the first siliconnitride film 6, while leaving “spacer” portions 11 of the second siliconnitride covering the sidewall surfaces of the layer stacks, as shown inFIGS. 1(c) and 2(c). Spacer portions 11 are typically tapered in widthfrom their lower ends proximate polysilicon layer 3 to essentially nowidth at their upper ends proximate silicon nitride “capping” layer 6.Suitable widths for the lower end portions of the tapered spacerportions 11 are from about 500 Å to about 2500 Å.

[0052] The combination of silicon nitride “capping” layer 6 and sidewallspacer portions 11 serves to effectively encapsulate tungsten gateelectrode contact layer 5 and prevent deleterious oxidation thereofduring subsequent high temperature treatments performed in an oxidizingambient, e.g., furnace annealing in an oxygen containing atmosphere at atemperature of from about 800° C. to about 950° C. for from about 30min. to about 60 min. As may be evident, the widths and densities(alternatively, porosities) of both silicon nitride layers are selectedin accordance with the subsequent processing conditions to effectivelypreclude entry of oxidants (e.g., O₂) thereinto for reaction withtungsten contact layer 5. In addition to the above consideration, theas-deposited thickness of the silicon nitride capping layer 6 should besufficiently thick to withstand further etching during subsequentprocessing steps.

[0053] Next, polysilicon layer 3 is etched away, as by reactive ionetching, using silicon nitride capping layer 6 as a self-aligned hardmask. The resulting structures are as shown in FIGS. 1(d) and 2(d). Forthe flash memory cell, since the silicon oxide and silicon nitridelayers of composite interpoly dielectric layer 8 act as an etch stop,another dry (e.g., a reactive ion) etch is performed to remove theexposed portions of the ONO composite dielectric layer 8 and polysiliconlayer 7 (poly 1), again using silicon nitride capping layer 6 as aself-aligned mask. Etch selectivity during this process is high againstsilicon nitride and therefore, the silicon nitride “capping” layer 6retains sufficient thickness to prevent oxidation of the tungstencontact layer 5 during any subsequent high temperature annealingprocessing, as may be seen from FIG. 2(e). A further technologicaladvantage attendant the inventive process wherein silicon nitride“capping” layer 6 remains over the tungsten contact layer throughoutprocessing is the ability to perform a high selectivity etch to removethe field oxide in a later step. Again, the combination of silicon“capping” layer 6 and sidewall spacer layer portions 11 effectivelyprevents oxidation of the tungsten contact layer 5 during any hightemperature processing associated therewith.

[0054] Referring now to FIGS. 1(e) and 2(e), a series of light andmedium dosage ion implantation steps are next performed to form activeregions of differing dopant density and profile in the semiconductorsubstrate 1, such as, but not limited to, source and drain regions 12and 13. In addition, a high temperature furnace annealing step at atemperature of from about 800° C. to about 1000° C., e.g., preferablyabout 900° C., is performed for from about 15 min. to about 60 min.,preferably about 30 min., between successive implantations of differingdosage in order to form a pre-low dosage implant layer at a thickness ofabout 75 Å. As indicated above, tungsten electrode contact layer 5 iseffectively prevented from oxidation during this step by virtue of thesilicon nitride encapsulating layers 6 and 11.

[0055] Following the dopant implantation steps for forming activeregions, such as source and drain regions 12 and 13, and with referenceto FIGS. 1(f) and 2(f), oxide spacer layer 14 is formed to a thicknessof from about 500 Å to about 2000 Å, preferably about 1000 Å, on theexposed surfaces of the layer stacks L₁ and L₂, as well as on theexposed surface of the substrate 1. In the case of the memory cell, theoxide layer 14 is selectively etched as shown in FIG. 2(f), using thesilicon nitride capping layer 6 as an etch stop.

[0056] Referring now to FIGS. 1(g) and 2(g), an additional layer ofoxide is then deposited on the side surfaces of oxide layer 14,resulting in the formation of thicker sidewall spacer layers 15, andoxide on the upper surface of the layer stack is removed by selectiveetching. In a further step, shown in FIGS. 1(h) and 2(h), source/drainN⁺ regions 16 and Vss connections are formed by ion implantation, inconventional manner.

[0057] Thus, by providing silicon nitride layers according to thepresent invention which effectively encapsulate the tungsten gateelectrode contact and remain in place essentially throughout allprocessing steps involving high temperature treatment in oxidizingambients, the problem of deleterious oxidation of the tungsten contactsis eliminated and sub-micron sized contacts having extremely low sheetresistance are, therefore, reliably obtained. Moreover, although in theillustrated embodiment, the inventive concept is applied to themanufacture of flash EEPROMS, the inventive method and structure of thepresent invention are applicable to all manner of semiconductor devicesemploying tungsten or tungsten-based contacts.

[0058] In the previous descriptions, numerous specific details are setforth, such as particular materials, structures, reactants, processes,etc., in order to provide a thorough understanding of the presentinvention. However, it should be recognized that the present inventioncan be practiced without resorting to the details specifically setforth. In other instances, well-known processing structures andtechniques have not been described in detail in order not tounnecessarily obscure the present invention.

[0059] Only the preferred embodiments of the present invention are shownand described herein. It is to be understood that the present inventionis capable of changes or modifications within the scope of the inventiveconcept as expressed herein.

What is claimed is:
 1. A method of manufacturing a semiconductor device,which method comprises the steps of: providing a semiconductor substratecomprising silicon and having a surface; sequentially forming over saidsubstrate surface a layer stack comprising: a gate oxide layer (a) onsaid substrate surface, an electrically conductive polysilicon layer (b)on said gate oxide layer, a barrier material layer (c) on saidpolysilicon layer, a tungsten layer (d) on said barrier material layer,and a silicon nitride layer (e) on said tungsten layer; selectivelyremoving portions of layers (c)-(e) to define a pattern therein exposingsidewall surfaces of said layers (c)-(e); selectively forming a siliconnitride layer (f) covering said exposed sidewall surfaces of said layers(c)-(e), whereby said tungsten layer (d) is encapsulated by thecombination of said silicon nitride layers (e) and (f) formed on theuppermost and sidewall surfaces thereof, respectively; selectivelyremoving portions of polysilicon layer (b) to define a pattern thereinexposing sidewall surfaces thereof in substantial vertical registry withsaid sidewall surfaces of layers (c)-(e); and annealing the thus-formedlayer stack at an elevated temperature in an oxidizing ambient, wherebysaid silicon nitride encapsulating layers (e) and (f) prevent oxidationof said tungsten layer (d) during said annealing.
 2. The method as inclaim 1, wherein said semiconductor device comprises a transistor, saidelectrically conductive polysilicon layer (b) comprises a gate electrodeof said transistor, said tungsten layer (d) comprises a gate electrodecontact, and the method comprises forming said layer stack on at least aperipheral portion of said substrate surface.
 3. The method as in claim2, further comprising: forming said layer stack on a central portion ofsaid substrate surface; and, after forming gate oxide layer (a) butprior to forming polysilicon layer (b): forming an electricallyconductive polysilicon layer (a′) on said gate oxide layer (a); andforming an interpoly dielectric layer (a″) on said polysilicon layer(a′); the method further comprising the step of selectively removingportions of polysilicon layer (a′) and interpoly dielectric layer (a″)to thereby expose sidewall surfaces thereof in substantial verticalregistry with said exposed sidewall surfaces of layers (b)-(e); whereinsaid semiconductor device comprises a flash-type EEPROM, saidpolysilicon layer (a′) comprises a floating gate electrode, saidpolysilicon layer (b) comprises a low sheet resistance control gateelectrode, and said tungsten layer (d) comprises a control gateelectrode contact.
 4. The method as in claim 3, comprising annealing byheating in an oxygen containing ambient at a temperature of from about800 ° C. to about 950 ° C. for from about 30 min. to about 60 min. 5.The method as in claim 3, comprising forming said gate oxide layer (a)at a thickness of from about 25 Å to about 150 Å.
 6. The method as inclaim 3, comprising forming said polysilicon layer (a′) at a thicknessof from about 250 Å to about 1000 Å.
 7. The method as in claim 3,comprising forming said interpoly dielectric layer (a″) at a thicknessof from about 50 Å to about 300 Å.
 8. The method as in claim 7, whereinsaid interpoly dielectric layer (a″) comprises a silicon oxide/siliconnitride/silicon oxide composite.
 9. The method as in claim 3, comprisingforming said polysilicon layer (b) at a thickness of from about 900 Å toabout 2500 Å.
 10. The method as in claim 3, comprising forming saidlayer (c) of barrier material at a thickness of from about 50 Å to about300 Å.
 11. The method as in claim 10, comprising depositing said layer(c) of barrier material comprising tungsten nitride by reactivesputtering of a tungsten target in a nitrogen-containing atmosphere. 12.The method as in claim 10, comprising depositing said layer (c) ofbarrier material comprising titanium nitride deposited by reactivesputtering of a titanium target in a nitrogen-containing atmosphere. 13.The method as in claim 3, comprising forming said layer (d) of tungstenat a thickness of from about 700 Å to about 4000 Å by a physical orchemical vapor deposition process.
 14. The method as in claim 3,comprising forming said layer (e) of silicon nitride on the uppersurface of tungsten layer (d) at a thickness of from about 150 Å toabout 1,000 Å.
 15. The method as in claim 3, comprising forming saidlayer (f) of silicon nitride on said sidewall surfaces of layers (c)-(e)at a width of from about 500 Å to about 2500 Å at its lower endproximate the substrate surface and tapering to essentially no width atits upper, distal end.
 16. The method as in claim 3, further comprisingforming source and drain regions at selected locations of the substratesurface.
 17. The method as in claim 16, further comprising forming atleast one layer of oxide covering at least the sidewall surfaces of saidlayer stack and said silicon nitride layer (f).
 18. A semiconductordevice, comprising: a semiconductor substrate comprising silicon andhaving a surface with at least one active device region formed thereinor thereon; a layer stack formed on said substrate over said at leastone active device region, said layer stack comprising, in sequence: agate oxide layer (a) on said substrate, an electrically conductivepolysilicon gate electrode layer (b) on said gate oxide layer, atitanium nitride or tungsten nitride barrier layer (c) on saidpolysilicon layer, a tungsten gate electrode contact layer (d) on saidbarrier layer, and a silicon nitride layer (e) on said tungsten layer,said layer stack being patterned to expose sidewall surfaces of layers(b)-(e); and a silicon nitride layer (f) covering said exposed sidewallsurfaces of layers (c)-(e), whereby said tungsten layer (d) isencapsulated by the combination of said silicon nitride layers (e) and(f) formed on the uppermost and sidewall surfaces thereof, respectively,thereby preventing oxidation of said tungsten layer (d) during annealingof said device structure at an elevated temperature in an oxidizingambient. thickness of about 100 Å to about 1500 Å.
 19. The semiconductordevice as in claim 18, comprising a transistor and said at least oneactive device region is formed at least at a peripheral portion of saidsemiconductor substrate.
 20. The semiconductor device as in claim 18,wherein said layer stack further comprises: an electrically conductivepolysilicon layer (a′) on said gate oxide layer (a), and a siliconoxide/silicon nitride/silicon oxide composite interpoly dielectric layer(a″) on said polysilicon layer (a′) and under said polysilicon layer(b), said polysilicon layer (a′) and said composite dielectric layer(a″) patterned to expose sidewall surfaces thereof in substantialvertical registry with the sidewall surfaces of layers (b)-(e) of saidlayer stack; wherein: said semiconductor device comprises a flash-typeEEPROM, said polysilicon layer (a′) comprises a floating gate electrode,said polysilicon layer (b) comprises a control gate electrode, and saidtungsten layer (d) comprises a control gate electrode contact.